With growing demand for flash memory in automotive, IoT, and consumer applications, as well as ever higher transfer rates and lower latency, the Cadence® Host Controller IP for xSPI offers up to 8 flash Serial Peripheral Interfaces (i.e., Octal SPI, HyperFlash, xSPI) to further increase the Serial Flash Memory throughput while providing backwards compatibility with single, dual, and quad I/O interfaces. The Host Controller IP for xSPI supports Serial Flash devices that comply to the following standards:
• JEDEC xSPI (JESD251) v1.0
• JESD216C rev. 0.6
• Octal SPI – manufactured by Micron and Macronix
• HyperFlash – manufactured by Cypress
• QSPI – multiple vendors supported
The Host Controller IP for xSPI connects to a systemon- chip (SoC) host through Arm® AMBA® AXI buses for data interfaces (Slave and Master) and APB bus for the register interface.
The integrated soft combo PHY enables the highest speed clock rates, eliminating the need to generate a reference clock based on the Flash memory clock.