Emerging high-performance applications demand increasingly fast read throughputs from NOR-flash memory devices. At the same time, the pin-count required to implement the memory subsystem should be restricted. The HyperBus flash controller was developed to satisfy the need for higher read/write performance while remaining sensitive to the pin-count constraints of modern microcontrollers. The HyperBus flash controller has the ability to satisfy the memory requirements for both volatile and nonvolatile memories in a large swath of high-performance applications.
The HyperBus flash Interface is a low pin count interface that achieves significantly higher perfor mance than legacy parallel and SPI interfaces for SPI based NOR flashes. This controller Interface involves a simple read/write protocol that is suitable for both memories and peripheral interfaces. Interestingly, this interface only requires an additional six pins more than the QSPI. The HyperFlash memories coupled with our Hyperbus flash controller provide a new standard for performance by delivering upto 333 MB/s using this 12-pin interface.
- Compatible with spansion hyperbus based memory products.
- 0 Wait State Write Burst Operation for HyperBus memory on AXI interface of up to 256 words.
- True Continuous Burst Read operation for HyperFlash on HyperBus memory interface.
- AXI-lite port for control registers accesses.
- Minimum Gap between two Read Operations for highest performance on HyperBus memory interface.
- Cache Line accesses for Execution-in-Place (XiP).
- HyperBus memory device clock of up to 166MHz.
- Up to 16 outstanding address support in AXI.
- Configurable Options
- Internal FIFO Depths is configurable
- AXI parameters configurable
- Design Attributes
- Highly modular design
- Clearly demarked clock domains
- Software control for key features
- Loopback for Debugging
- Configurable RTL Code
- HDL based test bench and behavioral models
- Test cases
- Protocol checkers, bus watchers and performance monitors
- Design Guide
- Verification Guide
Block Diagram of the Hyperbus Flash Memory Controller IP Core