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Low Latency & size Interlaken core for ASIC or FPGA, up to 1,000Gbps, 32 lanes, 112G/lane
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HyperLength FFT
RFEL’s Hyperlength FFT design allows the implementation of very long transforms in FPGA by utilising external RAM. The architecture uses a pair of pipeline FFTs to implement an N point and an M point DFT, which, together with data re-ordering and twiddle factor application, form an (N x M)-point FFT. External RAM is used to perform the required data re-ordering stages. Twiddle factors are generated arithmetically using logic within the FPGA rather than being stored in external memory.
The driving factor behind the FPGA choice for the Hyperlength FFT is often not the resource required to implement the processing, but the bandwidth limits of the available external RAM devices and the I/O required connecting them.
The driving factor behind the FPGA choice for the Hyperlength FFT is often not the resource required to implement the processing, but the bandwidth limits of the available external RAM devices and the I/O required connecting them.
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Block Diagram of the HyperLength FFT IP Core
