Wave Computing s MIPS I6500 multiprocessor core extends the variety and scalability of the company s “off-the-shelf” licensable IP cores based on the proven and respected MIPS64 architecture, and delivering a compelling solution for heterogeneous computing.
This IP core offering provides key features to deliver “heterogeneous inside and out”, many core/multi-cluster scalable processing, and real-time deterministic execution – even when utilizing its support for hardware virtualization – making the I6500 family one of the most scalable, flexible and powerful IP cores in the industry.
The flexibility and scalability makes it ideal for the growing and varied requirements of heterogeneous computing applications, including advanced driver assistance systems (ADAS) and autonomous driving, high performance networking, machine learning, drones, industrial automation, security, and video analytics.
Like the I6400 IP core family before it, the foundation of the I6500 family is a multi-threaded superscalar CPU core which, in a single multi-core cluster, can utilize up to six cores. As the basis for its “heterogeneous inside” capabilities, each core in the cluster can now be individually configured as part of silicon design to optimize and align the performance, area and power of the total solution to application requirements. This includes varying the number of hardware threads, the size of each L1 cache, as well as optional inclusion of a SIMD/FPU processing unit.
Data ScratchPad RAM (SPRAM) per core, up to four AXI ports for low latency peripherals or cluster-level SPRAM, and inter-thread communications (ITC) support are added (and optional). These features support both deterministic, low-latency operation and fast path messaging in embedded systems, and implementations of high-performance networking/data processing applications operating as a complement to the standard cached memory system.
The combination of simultaneous multi-threading with hardware virtualization in the I6500 processor enables multiple execution environments to run simultaneously, isolated from each other, with zero context switch overhead.