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I2C Bus Interface

The serial controller interface (Single Master) core uses a two-wire bus for communicating between integrated circuits or standard peripherals like smart LCDs and keypads. The core contains the entire physical and data link layers, allowing it to handle bus timing and
frame generation/extraction, and thus reducing overhead from the system application. A flexible parallel interface is used for on-chip data transfer, facilitating integration of the iniSCI core to the rest of the system.

Features

I2C-Compatible
Single Master
Programmable Baud Rate Generator (390 - 100k bps with 1us Clock Enable)
2 MHz Clock Required for 100k bps
Automatic Incremented Address Pointer
Message Acknowledgement
Customizable for Special Requirements

Benefits

iniSCI is modular structured into a BitSync bus interface, receiver, transmitter, and framer modules. This modular structure facilitates an understanding of the core’s functionality, thus simplifying customization.

Deliverables

VHDL or Verilog RTL Source Code
Functional Testbench
Synthesys Script
Data Sheet
User Guide
Hotline Support by means of phone, fax and e-mail

Block Diagram of the I2C Bus Interface IP Core

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I2C IP

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