I2C Bus Interface - Master/Slave
The DI2CMS is technology independent, that's why a VHDL or VERILOG design can be implemented in a variety of process technologies. Furthermore, it can be also completely customized in accordance to the customer's needs.
The DI2CMS is delivered with fully automated testbench and complete set of tests, allowing easy package validation at each stage of SoC design flow.
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I2C IP
- I2C Host / Device Bus Controller
- DO-254 I2C Master Serial Interface Controller 1.00a
- A 28nm Wirebond IO library with dynamically switchable 1.8V/ 3.3V GPIO, 5V I2C open-drain, 1.8V & 3.3V analog, OTP program cell, and HDMI & LVDS protection macros - featured across a variety of metal stack and pad configuration options
- A 22nm Wirebond IO library with dynamically switchable 1.8V/3.3V GPIO, 3.3V I2C open-drain, & analog cells
- A 65nm Wirebond IO library with 1-3.3V GPIO, 3.3V pulse-width modulation cell, I2C & SVID open-drain, 3.3V & 5V analog and OTP program cell
- Open-drain I2C and SMBUS, DDC, CEC & HPD IO offerings in TSMC Technologies