English
You are here:
I2C Bus Interface - Master with FIFO
The DI2CM-FIFO core provides an interface between a microprocessor/microcontroller and I2C bus. It can work as:
a master transmitter or
master receiver
depending on a working mode determined by the microprocessor/microcontroller. The DI2CM-FIFO core incorporates all features required by the latest I2C specification, including clock synchronization, arbitration, multi-master systems, and high-speed transmission mode. Built-in timer allows operation from a wide range of clk frequencies. The DI2CM-FIFO is a technology independent design that can be implemented in variety of process technologies.
a master transmitter or
master receiver
depending on a working mode determined by the microprocessor/microcontroller. The DI2CM-FIFO core incorporates all features required by the latest I2C specification, including clock synchronization, arbitration, multi-master systems, and high-speed transmission mode. Built-in timer allows operation from a wide range of clk frequencies. The DI2CM-FIFO is a technology independent design that can be implemented in variety of process technologies.
Features
- Conforms to v.6.0 of the I2C specification
- Master operation Master transmitter
- Master receiver
- Support for all transmission speeds
- Standard (up to 100 kb/s)
- Fast (up to 400 kb/s)
- Fast Plus (up to 1 Mb/s)
- High Speed (up to 3,4 Mb/s)
- ULTRA-FAST (up to 5 Mb/s)
- Configurable FIFO size up to 256 Bytes
- Configurable SDA/SCL glitch filter
- Software programmable SDA/SCL bus timings
- Arbitration and clock synchronization
- Support for multi-master systems
- Support for both 7-bit and 10-bit addressing formats on the I2C bus
- Interrupt generation
- Allows operation from a wide range of input clock frequencies (build-in 12-bit clock timer)
- Available system interface wrappers:
- AMBA – APB Bus
- Altera Avalon Bus
- Xilinx OPB Bus
- Fully synthesizable
- Static synchronous design
- Positive edge clocking and no internal tri-states
- Scan test ready
Benefits
- Getting a sillicon proven IP
- Rapid prototyping and time-to-market reduction
- Design risk elimination
- Development costs reduction
- Full customization
- Technological independence (VHDL and Verilog)
- Global sales network
- Professional service
Applications
- Embedded microprocessor boards
- Consumer and professional audio/video
- Home and automotive radio
- Low-power applications
- Communication systems
- Cost-effective reliable automotive systems
View I2C Bus Interface - Master with FIFO full description to...
- see the entire I2C Bus Interface - Master with FIFO datasheet
- get in contact with I2C Bus Interface - Master with FIFO Supplier
I2C
- TSMC based IO & ESD solutions supporting GPIO, I2C,RGMII, SD, LVDS, HDMI & analog/RF across multiple technology nodes
- A 28nm Wirebond IO library with dynamically switchable 1.8V/ 3.3V GPIO, 5V I2C open-drain, 1.8V & 3.3V analog, OTP program cell, and HDMI & LVDS protection macros - featured across a variety of metal stack and pad configuration options
- A 16nm/12nm Flip-Chip IO library with dynamically switchable 1.8V/3.3V GPIO, 5V I2C open-drain, 5V OTP and 1.8V / 3.3V analog
- A 22nm Wirebond IO library with dynamically switchable 1.8V/3.3V GPIO, 3.3V I2C open-drain, & analog cells
- A 130nm Wirebond IO library with 3.3V GPIO, LVDS TX & RX, 3.3V I2C open-drain, analog cell and OTP program cell
- Open-drain I2C and SMBUS, DDC, CEC & HPD IO offerings in TSMC Technologies