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I2C Bus Interface - Master with FIFO
The DI2CM-FIFO core provides an interface between a microprocessor/microcontroller and I2C bus. It can work as:
a master transmitter or
master receiver
depending on a working mode determined by the microprocessor/microcontroller. The DI2CM-FIFO core incorporates all features required by the latest I2C specification, including clock synchronization, arbitration, multi-master systems, and high-speed transmission mode. Built-in timer allows operation from a wide range of clk frequencies. The DI2CM-FIFO is a technology independent design that can be implemented in variety of process technologies.
a master transmitter or
master receiver
depending on a working mode determined by the microprocessor/microcontroller. The DI2CM-FIFO core incorporates all features required by the latest I2C specification, including clock synchronization, arbitration, multi-master systems, and high-speed transmission mode. Built-in timer allows operation from a wide range of clk frequencies. The DI2CM-FIFO is a technology independent design that can be implemented in variety of process technologies.
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I2C IP
- I2C Master / Slave Bus Controller
- I2C Controller
- I2C Slave
- A 22nm Wirebond IO library with dynamically switchable 1.8V/3.3V GPIO, 3.3V I2C open-drain, & analog cells
- A 130nm Wirebond IO library with 3.3V GPIO, LVDS TX & RX, 3.3V I2C open-drain, analog cell and OTP program cell
- Open-drain I2C and SMBUS, DDC, CEC & HPD IO offerings in TSMC Technologies