I2C Master Controller
Features
- Supports 3 transmission speeds (100 kbps, 400 kbps, 3.5 Mbps).
- Programmable clock frequency.
- Programmable acknowledge bit.
- RAM data packet buffer included with parameterized length.
- Interrupt driven data transfers.
- Supports clock stretching and wait state generation.
- Start-bit, Stop-bit, Repeated start-bit and acknowl-edge-bit
- generation.
- Multi-master operation.
- 8051 microprocessor I/F supported.
- Fully synchronous design, using single clock.
- Silicon proven in ASIC and FPGA technologies for a variety of
- applications.
Deliverables
- Fully commented synthesizable VHDL or Verilog source code or FPGA netlist.
- VHDL or Verilog test benches and example configura-tion files.
- Comprehensive technical documentation.
- Technical support.
Block Diagram of the I2C Master Controller IP Core

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