English
You are here:
I2C Master/Slave Controller Core IP
I2C Master/Slave Controller core implements a bidirectional serial interface compatible with the NXP’s I2C bus specification and supports all transfer modes from and to the I2C bus.
I2C is a bidirectional, two-wire serial bus that is used to attach low-speed peripherals to a motherboard, embedded system or mobile. All I2C-bus compatible devices incorporate an on-chip interface which allows them to communicate directly with each other via the I2C-bus.
I2C is a bidirectional, two-wire serial bus that is used to attach low-speed peripherals to a motherboard, embedded system or mobile. All I2C-bus compatible devices incorporate an on-chip interface which allows them to communicate directly with each other via the I2C-bus.
Features
- Compatible with I2C Bus Specification Version 2.1
- Supports 7-bit addressing format
- Supports programmable time out feature
- AMBA 2.0 compliant APB Bus Interface
- Programmable as I2C Master and Slave modes
- Supports both Interrupt and non interrupt data transfers
View I2C Master/Slave Controller Core IP full description to...
- see the entire I2C Master/Slave Controller Core IP datasheet
- get in contact with I2C Master/Slave Controller Core IP Supplier
I2C
- APB I2C master and slave
- I2C Bus Interface - Master with FIFO
- A 16nm/12nm Flip-Chip IO library with dynamically switchable 1.8V/3.3V GPIO, 5V I2C open-drain, 5V OTP and 1.8V / 3.3V analog
- A 22nm Wirebond IO library with dynamically switchable 1.8V/3.3V GPIO, 3.3V I2C open-drain, & analog cells
- A 65nm Wirebond IO library with 1-3.3V GPIO, 3.3V pulse-width modulation cell, I2C & SVID open-drain, 3.3V & 5V analog and OTP program cell
- A 130nm Wirebond IO library with 3.3V GPIO, LVDS TX & RX, 3.3V I2C open-drain, analog cell and OTP program cell