I2C Master / Slave Controller w/FIFO (APB Bus)

Features

• I2C Master / Slave with Parameterized FIFO:
• Targets embedded processors with high performance algorithm requirements, by independently controlling the Transmit or Receive of bytes of information:
• For Transmits, the processor writes the Slave Address & bytes of information into the FIFO, sets a start control bit, and waits for an interrupt or polls a status bit signaling completion
• For Receive, the processor writes the Slave Address into the DB-I2C-MS-AHB, enables the controller, and waits for an interrupt or polls a status bit signaling completion. The processor then reads the bytes of information from the FIFO.
• Small VLSI footprint
• Master Controller Modes:
• Master – Transmitter
• Master – Receiver
• Slave Controller Modes:
• Slaver – Transmitter
• Slave – Receiver
• Multi-Master, Clock Synchronization, Arbitration, SCL held low by Slave, & Repeated Start capabilites
• Parameterized FIFO depth for higher performance. Optional 16 or 32-bit processor interface
• Supports three I2C bus speeds:
• Standard mode (100 Kb/s)
• Fast mode (400 Kb/s)
• Fast mode plus (1 Mbit/s)
• 8 sources of internal interrupts with masking control
• Compliance with AMBA AXI and I2C specifications:
• AMBA AHB Protocol Specification (V2.0)
• Philips/NXP – The I2C-Bus Specification, Version 2.1, January 2000 and NXP Rev 0.3 19 June 2007
• Fully-synchronous, synthesizable Verilog or VHDL RTL core, with rising-edge clocking, no gated clocks, and no internal tri-states, for easy integration into FPGA or ASIC design flows.

Benefits

• The DB-I2C-MS-APB Controller IP Core targets embedded processor applications with high performance algorithm requirements. While most I2C controllers require high processor interaction involvement, the DB-I2C-MS-APB contains a parameterized FIFO and Finite State Machine Control for the processor to off-load the I2C transfer to the DB-I2C-MS-APB Controller. Thus, while the DB-I2C-MS-APB is busy, independently controlling the I2C Transmit or Receive transaction of data, the processor can go off and complete other tasks.

Deliverables

• Verilog or VHDL RTL Source or technology-specific netlist.
• Comprehensive testbench suite with expected results.
• Synthesis scripts.
• Installation & Implementation Guide.
• Technical Reference Manual.

• see the entire I2C Master / Slave Controller w/FIFO (APB Bus) datasheet
• get in contact with I2C Master / Slave Controller w/FIFO (APB Bus) Supplier