The Digital Blocks DB-I2C-S-SCL-CLK-APB Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC or other high performance microprocessor via the AMBA 2.0 APB System Interconnect Fabric to an I2C Bus. The I2C is a two-wire bidirectional interface standard (SCL is Clock, SDA is Data) for transfer of bytes of information between two or more compliant I2C devices.
The DB-I2C-S-SCL-CLK-APB, in the I2C Slave Controller Core managing the I2C protocol & physical layer, contains no free running clock, while interfacing through dual-clock FIFOs to the AMBA APB Bus, for a low power, low noise Microprocessor interface to the I2C Bus. The I2C Slave Controller Core runs off the external SCL clock while the APB side off the APB Clock.
The DB-I2C-S-SCL-CLK is a member of Digital Blocks DB-I2C Controller IP Core family, which includes I2C Master/Slave, I2C Master-only, and I2C Slave-only configurations.
- I2C Slave Controller - Implements Slave-only protocol for smaller VLSI footprint, for applications requiring Slave–Receiver and Slave–Transmitter capability
- SCL Clock only for low power, low noise applications requiring configuration & management of User Registers
- 7- or 10-bit addressing, General Call, SCL Low Wait States
- Supports five I2C bus speeds:
- Standard mode (100 Kb/s)
- Fast mode (400 Kb/s)
- Fast mode plus (1 Mbit/s)
- Ultra fast mode (5 Mbit/s)
- Hs-mode (3.4 Mbit/s)
- Compliance with I2C specifications:
- Philips – The I2C-Bus Specification, Version 2.1, January 2000
- NXP UM10204 Rev 6 – 4 April 2014 Specification
- Fully-synchronous, synthesizable Verilog RTL core. Easy integration into FPGA or ASIC design flows.
- Verilog RTL Source or technology-specific netlist.
- Comprehensive testbench suite with expected results.
- Synthesis scripts.
- Installation & Implementation Guide.
- Technical Reference Manual.
Block Diagram of the I2C Slave Controller - Low Power, Low Noise Config with APB Interface