The Digital Blocks DB-I2C-S-APB / DB-I2C-S-AHB / DB-I2C-S-AXI / DB-I2C-S-AVLN Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC,NIOS II or other high performance microprocessor via the AMBA APB or AHB or AXI-Lite or Altera Avalon System Interconnect Fabric to an I2C Bus. The I2C is a two-wire bidirectional interface standard (SCL is Clock, SDA is Data) for transfer of bytes of information between two or more compliant I2C devices, typically with a microprocessor behind the master controller and one or more master / slave or slave devices.
Digital Blocks offers a I2C Controller Slave only function with FIFOF and interface to APB / AHB / AXI-lite / Avalon Interconnect. This enables a Microprocessor via the FIFO and DB-I2C control to interfaces as a I2C Slave device to ttransfers data with an external I2C master.
In addition, besides interfacing to a CPU, the I2C Slave Controllers can DMA transfer blocks of data directly between System Memory or Registers and the I2C Bus.
- I2C Slaver only with Parameterized FIFO:
- Targets embedded processors with high performance algorithm requirements, by independently controlling the Transmit or Receive of bytes of information.
- Small VLSI footprint
- Slave Controller Modes:
- Slave – Transmitter
- Slaver – Receiver
- SCL held low by Slave, & Repeated Start capabilites
- Parameterized FIFO depth for higher performance. Optional 16 or 32-bit processor interface
- Supports two I2C bus speeds:
- Standard mode (100 Kb/s)
- Fast mode (400 Kb/s)
- Fast mode plus (1 Mbit/s)
- 8 sources of internal interrupts with masking control
- Compliance with AMBA 2.0 and I2C specifications:
- AMBA Specifications - APB, AHB, AHB-lite, AXI-lite Bus and Avalon Bus
- Philips/NXP – The I2C-Bus Specification, Version 2.1, January 2000 and NXP Rev 0.3 19 June 2007
- Fully-synchronous, synthesizable Verilog or VHDL RTL core, with rising-edge clocking, no gated clocks, and no internal tri-states, for easy integration into FPGA or ASIC design flows.
- The DB-I2C-S Controller IP Core targets embedded processor applications with high performance algorithm requirements. While most I2C controllers require high processor interaction involvement, the DB-I2C-S contains a parameterized FIFO and State Machine Control for the processor to off-load the I2C transfer to the DB-I2C-S Controller. Thus, while the DB-I2C-S is busy, independently participating in a I2C Transmit or Receive transaction of data, the processor can go off and complete other tasks. Note that the Slave only capability of the DB-I2C-S-AHB adds to its small VLSI footprint requirements. Note further that Digital Blocks offers a DB-I2C-M Master only function IP Core, to compliment the DB-I2C-S.
- Verilog RTL Source or technology-specific netlist.
- Comprehensive testbench suite with expected results.
- Synthesis scripts.
- Installation & Implementation Guide.
- Technical Reference Manual.