The I2C Controller IP Core implements an I2C Slave Controller, with a user parameterized Register Array or Memory (i.e SRAM / FIFO) or any Peripheral connecting on an AHB / APB / AXI / Avalon Bus for embedded user I/O Control & Status or block data transfers within an ASIC / ASSP / FPGA device. The I2C Controller implements the Slave-Transmit and Slave-Receive protocol according to the Philips I2C-Bus Specification, Version 2.1 as well as the NXP Rev .5 October 9, 2012 Specification.
- I2C Slave Controller - Implements Slave-only protocol for smaller VLSI footprint, for applications requiring Slave–Receiver and Slave–Transmitter capability
- Autonomous I2C Slave Controller:
- No local CPU host required
- No configuring of control/status registers
- 7- or 10-bit I2C Slave addressing, SCL Low Wait States
- Supports five I2C bus speeds:
- Standard mode (100 Kb/s)
- Fast mode (400 Kb/s)
- Fast mode plus (1 Mbit/s)
- Ultra fast mode (5 Mbit/s)
- Hs-mode (3.4 Mbit/s)
- Compliance with I2C specifications:
- Philips – The I2C-Bus Specification, Version 2.1, January 2000
- NXP Rev .5 October 9, 2012
- Fully-synchronous, synthesizable Verilog RTL core. Easy integration into FPGA or ASIC design flows.
- Verilog RTL Source or technology-specific netlist.
- Comprehensive testbench suite with expected results.
- Synthesis scripts.
- Installation & Implementation Guide.
- Technical Reference Manual.
Block Diagram of the I2C Slave Controller with User Register Array / Memory / FIFO / AMBA Interface