The Digital Blocks DB-I2C-SMBus-MS-AMBA Controller IP Core is an I2C/SMBus Master/Slave Controller, interfacing a microprocessor via the AMBA AXI, AHB, or APB Bus to an I2C/SMBus Interconnect. Both I2C and SMBus protocols are supported.
- The DB-I2C-SMBus-MS-AMBAI Controller IP Core targets embedded processor applications with high performance algorithm requirements. While most I2C/SMBus controllers require high processor interaction involvement, the DB-I2C-SMBus-MS-AMBA contains a parameterized FIFO and Finite State Machine Control for the processor to off-load the I2C/SMBus transfer to the DB-I2C-SMBus-MS-AMBA Controller. Thus, while the DB-I2C-SMBus-MS-AMBA is busy, independently controlling the I2C/SMBus Transmit or Receive transaction of data, the processor can go off and complete other tasks.
- Verilog or VHDL RTL Source or technology-specific netlist.
- Comprehensive testbench suite with expected results.
- Synthesis scripts.
- Installation & Implementation Guide.
- Technical Reference Manual.
Block Diagram of the I2C/SMBus Master/Slave Controller w/FIFO (AXI/AHB/APB)