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I2S IP core
The use of IP cores in ASIC, FGPA and system-on-chip (SoC) designs has become a critical methodology as companies struggle to address the need for rapid prototyping
and production. Reusable, drop-in components with predefined functionality, IP cores speed the design cycle, increase design quality and allow a greater degree of innovation, enabling companies to reduce design costs and create market differentiation.
This IP core has been designed and verified using Cadence state-of-the-art EDA tools, methodology and recommended design and verification flow.The use of IP cores in ASIC, FGPA and system-on-chip
(SoC) design has become a critical methodology as
companies struggle to address the need for rapid proto-
typing and production. Reusable, drop-in components
with pre-defined functionality, IP cores speed the
design cycle, increase design quality and allow a greater
degree of innovation, enabling companies to reduce
design costs and create market differentiation.
HDL Design House provides a set of IP cores for reuse
along with IP core customization services to meet spe-
cific customer needs. Optimized for today’s SoC designs,
these IP cores are supported with full documentation,
including architectural and micro-architectural specifi-
cations, synthesis scripts, detailed test plans, test case
definitions and test bench descriptions.
and production. Reusable, drop-in components with predefined functionality, IP cores speed the design cycle, increase design quality and allow a greater degree of innovation, enabling companies to reduce design costs and create market differentiation.
This IP core has been designed and verified using Cadence state-of-the-art EDA tools, methodology and recommended design and verification flow.The use of IP cores in ASIC, FGPA and system-on-chip
(SoC) design has become a critical methodology as
companies struggle to address the need for rapid proto-
typing and production. Reusable, drop-in components
with pre-defined functionality, IP cores speed the
design cycle, increase design quality and allow a greater
degree of innovation, enabling companies to reduce
design costs and create market differentiation.
HDL Design House provides a set of IP cores for reuse
along with IP core customization services to meet spe-
cific customer needs. Optimized for today’s SoC designs,
these IP cores are supported with full documentation,
including architectural and micro-architectural specifi-
cations, synthesis scripts, detailed test plans, test case
definitions and test bench descriptions.
Features
- IP core meets the Philips Inter-IC Sound bus specification
- Supports configurable 8/16/24/32 bit DAC/ADC resolution
- Supports Master/Slave and Receiver/Transmitter modes
- Two sets of SCK (SCLK) and WS strobes:
- One for all transmitters
- One for all receivers
- 32-bit parallel AMBA APB processor bus (other custom specific buses can also be provided upon request).
- Configurable internal FIFO's (one for all transmitter channels and one for all receiver channels)
- Audio sampling capabilities:8, 16, 24, 32, 44.1, 48; 88.2; 96; 176.4; 192kHz
- The I2S Bus Interface may operate in one of the following four configurations:
- I2S – Philips mode
- Left Justified mode
- Right Justified mode
- DSP mode
- Mode of operation for each channel can be set in the single configuration register
- IRQ driven by the I2S bus events
Benefits
- User configurable formaximumflexibility
- Easy to integrate into complex SoC designs
- Shortens development cycles
- Speeds time tomarket of new products
- Enables innovation andmarket differentiation
Deliverables
- Verilog RTL source code
- Functional specification
- Microarchitecture specification with detailed core integration guide
View I2S IP core full description to...
- see the entire I2S IP core datasheet
- get in contact with I2S IP core Supplier
