I2S Master interface provides full support for the two-wire I2S synchronous serial interface, compatible with I2S specification. Through its I2S compatibility, it provides a simple interface to a wide range of low-cost devices. I2S Master IIP is proven in FPGA environment. The host interface of I2S can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.
- Compliant with ISO/IEC 7816-3 Specification.
- Full IEC7816-3 Slave functionality.
- Supports all functions for complete smart card sessions, including
- ->Card activation and deactivation
- ->Cold/warm reset
- ->Answer to Reset (ATR) response reception
- ->Data transfers to and from the card
- Supports adjustable clock rate and bit (baud) rate.
- Supports configurable automatic byte repetition.
- Supports commonly used communication protocols
- ->T = 0 for asynchronous half-duplex character transmission, and
- ->T = 1 for asynchronous half-duplex block transmission
- Fully synthesizable
- Static synchronous design
- Positive edge clocking and no internal tri-states
- Scan test ready
- Simple interface allows easy connection to microprocessor/microcontroller devices
- Single Site license option is provided to companies designing in a single site.
- Multi Sites license option is provided to companies designing in multiple sites.
- Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
- Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
- The I2S Master interface is available in Source and netlist products.
- The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
- Easy to use Verilog Test Environment with Verilog Testcases.
- Lint, CDC, Synthesis, Simulation Scripts with waiver files.
- IP-XACT RDL generated address map.
- Firmware code and Linux driver package.
- Documentation contains User's Guide and Release notes.