The logiI2S IP core from Xylon's logicBRICKS™IP library is a module for I2S audio data receiving and/or transmitting. The logiI2S IP's RX and TX submodules are I2S masters only.
The logiI2S is, like the other IP cores from Xylon logicBRICKS™ IP library, fully embedded into Xilinx Platform Studio (XPS) and the EDK.
Therefore it can be easily customized and tuned for optimal slice consumption and features set.
- Configurable structure
- OPB V2.0 bus interface for access into internal registers
- PLB V3.4 bus interface for off-chip memory access
- Adjustable memory interface width 16, 32, or 64 bits
- single master clock for I2S timings generation
- Dividable master clock by an embedded divisor
- Adjustable sampling frequency
- Configurable on-chip FIFO buffers
- Supports various audio sample widths: 8, 16, 18, 20, and 24 bits
- Configurable size of off-chip memory buffers
- Buffers status monitoring
- optimized for low slice count
- prepared for Xilinx Platform Studio (XPS) and the EDK