768x39 Bits OTP (One-Time Programmable) IP, TSMC 55ULP 0.9V–1.2V / 2.5V
I3C Host Controller
The main purpose of MIPI I3C is threefold:
To standardize sensor communication
Reduce the number of physical pins used in sensor system integration and
Support low-power, high-speed and other critical features that are currently covered by I2C and SPI.
View I3C Host Controller full description to...
- see the entire I3C Host Controller datasheet
- get in contact with I3C Host Controller Supplier
Block Diagram of the I3C Host Controller IP Core
I3C IP
- MIPI I3C PHY - TSMC (12nm, 7nm, 5nm, and 22nm) - GF 12nm
- TSMC 3nm (N3E) 1.2V/1.8V I3C Libraries
- TSMC 3nm (N3E) 1.2V/1.8V I3C Libraries, multiple metalstacks
- MIPI I3C controller delivers high bandwidth and scalability for integration of multiple sensors
- TSMC 5nm (N5) 1.2V/1.8V I3C Libraries
- TSMC 4nm (N4P) 1.2V/1.8V I3C Libraries