The Digital Blocks DB-I3C-MS-APB Controller IP Core interfaces a microprocessor via the AMBA APB Bus to an I3C Bus, compliant to the MIPI I3C – Improved Inter Integrated Circuit specification.
The I3C is a two-wire bidirectional interface standard (SCL is Clock, SDA is Data) for transfer of bytes of information between two or more compliant I3C devices as well as legacy I2C Slave devices, typically with a microprocessor behind the Master/Slave controller and one or more Master or slave devices on the I3C bus.
Digital Blocks offers I3C Controller Master/Slave, Master only, and Slave only IP with AXI / AHB / APB Interfaces. In addition, besides interfacing to a CPU, the I3C Controllers can transfer blocks of data directly between System Memory or Registers and the I3C Bus.
- Master / Slave MIPI I3C Controller
- Supports following I3C bus speeds:
- Single Data Rate (SDR) - up to 12.5 MHz
- High Data Rate (HDR) (Optional)
- I3C Communications Support:
- I3C SDR / Broadcast / Direct Messages
- Legacy I2C Message
- I3C HDR Mode (optional)
- I3C compliant features:
- Dynamic Addressing Assignment
- Secondary Master Function
- In-Band Interrupt
- Hot-Join Mechanism
- Synchronous/ Asynchronous Timing Stamping
- I3C Characteristics Registers
- Common Command Codes (CCCs)
- Parameterized FIFO memory for off-loading the I3C transfers from the processor
- Compliance with I3C, I2C, and AMBA specifications
- Fully-synchronous, synthesizable Verilog RTL core, Low Power Design
- Verilog RTL Source or technology-specific netlist.
- Comprehensive testbench suite with expected results.
- Synthesis scripts.
- Installation & Implementation Guide.
- Technical Reference Manual.
Block Diagram of the I3C Master / Slave Controller w/FIFO (APB Bus)