ASTC’s I3C Slave Core provides a slave interface for the following protocols:
- I2C standard mode (100kbps)
- I2C fast mode (Fm, 400kbps) and fast-mode plus (Fm+, 1Mbps)
- I2C high-speed mode (3.4Mbps)
- I3C single data rate (SDR, up to 12.5Mbps)
- Protocol engine implements the following I3C CCC commands: ENEC, DISEC, ENTAS0, RSTDAA, SETDAA, SETMWL, SETMRL, GETMWL, GETMRL, GETPID, GETBCR, GETDCR, GETSTATUS, GETMXDS, XTIME
- XTIME ST, DT, TPH, and TU subcommands for timing control of a synchronous system
- Dynamic address assignment, plus I2C legacy addressing
- In-band Interrupts with configurable payload size
- I3C error checking and recovery
- Slave interface signals for private messages and CCC command data
- ASTC’s I3C Slave Core implements I3C protocol sequencing and command processing. It provides a simple interface for a device to transfer data over I3C. Legacy I2C protocols are supported transparently.
- The following list of deliverables are included:
- Synthesizable SystemVerilog RTL
- Module Test Suite
- Integration Guide
- The MIPI I3C interface is an evolutionary standard that improves upon the features of I²C, while maintaining backward compatibility and is intended for use as a single interface that can be used for any sensor.
- This standard offers a flexible multi-drop interface between the host processor and peripheral sensors to support the growing usage of sensors in embedded systems. The main purpose of MIPI I3C is threefold:
- to standardize sensor communication,
- reduce the number of physical pins used in sensor system integration and
- support low-power, high-speed and other critical features that are currently covered by I²C and SPI.
Block Diagram of the I3C Slave IP Core