Designed for audio clock generation, this PLL integrates a phase frequency detector (PFD), a loop filter (LP), a voltage control oscillator (VCO), a current reference, three programmable dividers and other supportive circuits.
The reference clock is either a crystal or an input clock from other sources and supports 8.192MHz/10MHz/12MHz/12.288MHz/13MHz/13.5MHz/19.2MHz/21.25MHz/24MHz/26MHz/27MHz/38.85MHz as reference.
The PLL supports 256*fs and 128*fs clock output, wherein fs is the audio system’s sample rate of 8kHz/11kHz/12kHz/16kHz/22kHz/24kHz/32kHz/44.1kHz/48kHz/96kHz/192kHz.
- Process: IBM 10SF 65nm CMOS process
- MOSFET device used: nfet, pfet, dgnfet, dgpfet
- Metal stack: 40-30-02-00+LB
- Supply voltage: 2.5v +/-10%; 1.0v+/-10%
- Output duty cycle: 45~55% (P=2/4/6/8/12/16/24)
- Current: <0.3mA
- Operating junction temperature: -40~125°C