IBM 65nm LVDS Receiver

The LVDS Receiver converts up to 10 pairs of LVDS data streams into 70-bit of CMOS data and then feeds the data to the logic core that can support Single-Link transmission with up to SXGA+ resolution, or Dual-Link transmission with up to UXGA resolution. This IP is suitable for Flat Panel Display applications.

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IBM 65nm LVDS Receiver IP

IBM 65nm LVDS Transmitter
IBM 65nm LVDS Transmitter
SMIC 65nm Low Leakage LVDS Receiver
LVDS Receiver, 1Gbps
LVDS Receiver - 931Mbps
1.5Gbps 20-Lane LVDS Receiver PHY IP (Silicon Proven in TSMC 28HPC+)

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