IEEE802.15.3c irregular LDPC(672,336), LDPC(672,504), LDPC(672,588) encoder and decoder.
The implementation provides: (a) High throughput. Datarates
higher than the raw data rates of single carrier (SC) PHY
mode, and high speed interface (HSI) PHY mode; (b) Low-power
consumption and logic controlled gated clocks; (c) High silicon
utilization and reduced gate count; and (d) Low error rates with
both fine and coarse signal quantization.
Please contact Continuous-bits for the other variant availability (LDPC(1440,1344) ).