Xilinx® offers the 100 Gigabit IEEE 802.3bj Reed-Solomon Forward Error Correction (RS-FEC) IP core for data center and enterprise applications. This core is designed to the IEEE 802.3bj-2014 specification and connects seamlessly to the Xilinx integrated or soft 100G Ethernet MAC IP on Virtex® UltraScale™.
- Low latency
- Supports 100 Gigabits
- Configuration and status bus
- Selectable AXI4-Lite interface for status output
- Transcode Bypass mode for direct access to RS-FEC encoder/decoder
- Example reference design demonstrating integrated 100G Ethernet IP with RS-FEC
- ECC RAM option