The PTP Hybrid Clock (HC) from NetTimeLogic is a combination of NetTimeLogic's PTP Transparent Clock (TC) and PTP Ordinary Clock (OC). It adds the Sync and Announce message processors to the design which allow synchronization of the clock according to IEEE1588 while keeping the timing aware frame forwarding feature of the TC. The OC will run in Slave or Master mode according to the configuration and Best-Master-Clock (BMC) algorithm. For resource optimization the OC can also be implemented as Slave-Only clock.
The HC is intercepting the path between an Ethernet PHY and an Ethernet core that forwards or handles Ethernet frames. Mostly this is used in daisy-chained networks. This allows message injection in parallel to data transfers from/to the Switching Core.
All datasets and algorithms are implemented completely in HW.
- Combined PTP Ordinary Clock and PTP Transparent Clock according to IEEE1588-2008
- Intercepts path between MAC and PHY
- Two (TC) plus one (OC) Port, used for daisy chaining or redundancy protocols
- Synchronization accuracy: +/- 25ns
- Support for Default Profile: Layer 2 (Ethernet) and Layer 3 (Ip) support
- Support for Power Profile: C37.238-2011 and C37.238-2017 including VLAN support
- Support for Utility Profile: including HSR and PRP tag handling
- Support for IEEE802.1AS-REV: including IEEE802.1CB tag handling
- One Step and Two Step support
- Peer to Peer (P2P) and End to End (E2E) delay measurement
- Master and Slave support
- Full line speed
- AXI4 Light register set or static configuration
- Datasets according to IEEE1588
- MII/GMII/RGMII Interface support (optional AXI4 stream for interconnection to 3rd party cores)
- Optional Management Message support
- Optional Signaling Message support
- Timestamp resolution with 50 MHz system clock: 10ns
- Hardware PI Servo
- Coprocessor handling the synchronization and residence time corrections according to IEEE1588 or IEEE802.1AS completely standalone in the core.
- No Software Stack required
- Source Code (not encrypted, not obfuscated)
- Reference Designs
- Testbench with Stimulifiles
- Configuration Tool
- Distributed data acquisition
- Ethernet based automation networks
- Test and measurement
Block Diagram of the IEEE1588 & IEEE802.1AS PTP Hybrid Clock (HC) core