TheIPC55000 is a full IEEE1588v2 (PTPv2) standard compliant Slave Ordinary Clock (OC) IP core for ASICs.
Comprised of innovative Sync over Packet Engine (SoPE), state-of-the-art clock synchronization algorithms suite and IEEE1588v2 protocol stack, the IPC55000 is requiring low CPU power and small silicon footprint. The IPC55000 achieves excellent clock synchronization performance including frequency synchronization, phase and Time of Day (ToD) alignment surmounting stringent packet switched networks (PSN) impairments making it perfect for applications in need for reducing total cost of ownership with high-performance clock synchronization and minimal overhead. The IPC55000 is designed for easy field upgrades to support future enhancements as well as future clock synchronization standards.
- IPCore version of IPC50000 IEEE1588v2 Master/Slave Ordinary Clock for ASICs
- Highly efficient logic with small silicon footprint
- Flexible interfaces
- Hybrid 1588/SyncE mode support
- ToD alignment error is better than ±1µsec on a managed 10-switch GbE network under ITU-T G.8261 conditions (*)
- Frequency accuracy is better than 16ppb on a managed 10-switch GbE network under ITU-T G.8261 conditions (*)
- Standard compliant Best Master Clock (BMC) algorithm
- Easy implementation of master redundancy
- Programmable clock output: 1.544MHz, 2.048MH, or 10MHz
- Upgradeable by software
- Excellent performance with low cost oscillator
- Easily integrates in existing and next generation designs
- Provides precision holdover
- Easy adding of enhancements and supporting emerging clock synchronization standards