IGALVDV05A is a 6-channel LVDS Transmitter PHY IP, which is used mainly in Flat-panel Display. It enables larger, higher resolution displays and lowers component counts without increasing power consumption, bus interconnect or overall cost.
There is an internal de-skew Phase Locked Loop (PLL) to pro-vide x7 / x10 clock for LVDS TX functions.
- Operating junction temperature: -40℃~125℃
- Total 6 channels; 5 data pairs and 1 clock pair by default
- LVDS Input clock operation frequency: 10MHz~150MHz(10:1)/200MHz(7:1)
- LVDS Output data rate: 70Mbps~1500Mbps
- LVDS Input 7:1 / 10:1 parallel to serial ratio
- Output common mode voltage: 0.9V to 1.2V
- Adjustable Tx Clock/Data output driving: 1.5mA ~ 5mA
- Power down mode
- Tri-state and power off for individual Tx Data/Clock output