IGAPLLV09 PLL-based clock generating IP integrates a voltage-controlled oscillator, a phase frequency detector, a charge pump, a loop filter, and three frequency dividers. The PLL optimizes the phase jitter performance with the benefits of limited current consumption and robust VCO architecture. The clock generator circuit incorporates de-skew, bypass and power-down modes, and has separated analog and digital power and grounds for ease of design.
The PLL incorporates several frequency dividers to generate various output frequencies for different applications. The power down mode is available to shut down the power of the PLL circuit. The bypass mode provides to bypass the output clock of PLL to the external reference clock.
- TSMC CLN12FFC/CLN16FFC 0.8V/1.8V Process
- Metal Scheme : 1P6M (2Xa1Xd_h_2Xe_vh)
- 1.8V analog supply operation and 0.8V digital supply operation
- 10 to 225 MHz reference input clock
- De-skew mode
- Power-down mode
- Bypass mode
- Lock detection function
- Chip area :270um x 240um