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Image Signal Processing (ISP) IP with WDR and 3D+2D noise reduction IP
The camera image signal processing core can be used in security camera, industrial camera, automobile camera, medical camera, mobile phone camera and DSC. Our camera image signal processing core produces high resolution, clear and sharp images by using intelligent and high-performance algorithm. The ISP core uses the minimum logic in spite of using the intelligent and complex algorithm. We can provide the core of the image size, speed, logic size and functions optimized at specific application. The ISP core is provided by Verilog source or FPGA netlist with the document and the testbench for developing FPGA and ASIC.
Features
- Support RGB Bayer progressive image sensor
- Support 8 ~ 16 bit Bayer input data
- Support image sensor of 256*256 ~ 8192*8192 size
- Lens Shading Correction
- Defect Pixel Correction (On the fly mode & Predetermined mode)
- High quality interpolation
- 2D noise reduction
- 3D Motion Adaptive noise reduction (HDR/Star version Only)
- Color correction by 3x3 matrix
- Gamma correction
- Shadow/Highlight compensation (WDR, back light compensation)
- 2D edge enhancement
- support AE, AF and AWB
- Support Saturation, contrast, brightness control and sepia, negative, solarization mode
Deliverables
- Deliverables comprise: RTL code; Test bench;
- Xilinx . Altera or Microsemi FPGA netlist; Algorithm Software;
- Documentation; Technical support.
Block Diagram of the Image Signal Processing (ISP) IP with WDR and 3D+2D noise reduction IP
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Camera ISP IP
- Camera SLVS-EC/sub-LVDS combo Receiver 2.5Gbps 8/12-Lane
- Camera 6-Mode Combo-Receiver 1.5Gbps 4/8/12/16-Lane
- 8-13M pixel sensor support High Quality Image Signal Processing (ISP) IP
- 5M pixel sensor support Image Signal Processing (ISP) IP
- 2MPixel sensor support Image Signal Processing(ISP) IP
- Camera SLVS-EC/MIPI D-PHY combo Receiver 2.5G/1.5Gbps 8/12-Lane