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AES Accelerator
The AES Accelerators implement the Advanced Encryption Standard (AES) algorithm, as specified in Federal Information Processing Standard (FIPS) Publication 197. The accelerators include I/O registers, encryption and decryption cores, and the logic for feedback modes and key scheduling.
Designed for fast integration, low gate count, and maximum performance, the AES Accelerators provide a reliable and cost-effective AES IP solution that is easy to integrate into SoC designs.
Designed for fast integration, low gate count, and maximum performance, the AES Accelerators provide a reliable and cost-effective AES IP solution that is easy to integrate into SoC designs.
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AES Accelerator IP
- AES (ECB-CBC-CFB-CTR-GCM), 1 Billion Trace DPA Resistant Cryptographic Accelerator Cores
- AES (ECB), 1 Billion Trace DPA Resistant Cryptographic Accelerator Cores
- INSIDE Secure SafeXcel-IP-61 High-Speed AES-GCM-GMAC Accelerator Family
- AES (ECB-CBC-CFB-CTR), 1 Billion Trace DPA Resistant Cryptographic Accelerator Cores
- INSIDE Secure Basic AES Engine
- INSIDE Secure 800G Multi-Channel MACsec Engine from Rambus