AES Key Wrap Accelerator

Features

• Wide bus interface (128 bit data, 256 bit keys) or 32 bit register interface.
• Key/KEK sizes: 128, 192 and 256 bits.
• Includes key scheduling hardware.
• Supported modes: Nist AES Key Wrap.
• Memory interface for key, intermediate and result data storage up to 4096 bits (Maximum supported input data block size is 512 bytes)
• Fully synchronous design.
• Low Speed, Medium Speed, High Speed versions.
• Support for two ECC (Error Correcting Code) bits from the external memory
• Multiple IV loading options
• Unwrap result verification
• Fully synchronous design

Benefits

• High-speed AES Key Wrap solution
• Silicon-proven implementation
• Fast and easy to integrate into SoCs
• Flexible layered design
• Complete range of configurations
• World-class technical support

Deliverables

• Documentation
• Hardware Reference and Programmer Manual
• Integration Manual
• Verification Specification
• Synthesizable Verilog RTL source code
• Self-checking RTL test bench, including test vectors and expected result vectors
• Simulation scripts
• Configurations:
• EIP-36b
• High-speed Encrypt/Decrypt
• 62k gates (excluding external memory)
• 11.6 bits/clk
• up to 400 MHz
• EIP-36d
• Medium-speed Encrypt/Decrypt
• 39k gates (excluding external memory)
• 3.88 bits/clk
• up to 450 MHz
• EIP-36f
• Low-speed Encrypt/Decrypt
• 33k gates (excluding external memory)
• 2.42 bits/clk
• up to 450 MHz

Applications

• Key encryption
• Key protection

• see the entire INSIDE Secure AES Key Wrap Engine datasheet
• get in contact with INSIDE Secure AES Key Wrap Engine Supplier