As part of INSIDE Secure’s award-winning silicon Intellectual Property (IP) product portfolio, the EIP-32 AES Engines implement the Advanced Encryption Standard (AES) algorithm, as specified in Federal Information Processing Standard (FIPS) Publication 197. The accelerators include I/O registers, encryption and decryption cores, and the logic for feedback modes and key scheduling.
Designed for fast integration, low gate count, and maximum performance, the AES Engines provide a reliable and cost-effective AES IP solution that is easy to integrate into SoC designs.
- Key sizes: 128, 192 and 256 bits.
- Key scheduling hardware.
- Low gate count version.
- Fully synchronous design
- High-speed AES solution
- Silicon-proven implementation
- Fast and easy to integrate into SoCs
- Flexible layered design
- Complete range of configurations
- World-class technical support
- Hardware Reference and Programmer Manual
- Integration Manual
- Verification Specification
- Synthesizable Verilog RTL source code
- Self-checking RTL test bench, including test vectors and expected result vectors
- Simulation scripts
- Low Speed
- 9.1k gates
- 2.46 bits/clk
- up to 1025 MHz