Switching regulator, inductor-based, PWM mode, high efficiency, DELTA standard
DES/3DES Accelerator
Designed for fast integration, low gate count, and maximum performance, the DES/3DES Engines provide a reliable and cost-effective DES/3DES IP solution that is easy to integrate into SoC designs.
Features
- Includes key scheduling hardware,
- Includes feedback mode logic, with support for:
- Available in two speed configurations, 4 or 8 bits per clock cycle
- Wide bus interface
- Basic operation,
- F8 confidentiality algorithm,
- F9 integrity algorithm,
- Automatic data padding mechanism for F9 algorithm,
- KASUMI encryption and decryption modes,
- Includes key scheduling hardware,
- Fully synchronous design
Benefits
- High-speed DES solution
- Silicon-proven implementation
- Fast and easy to integrate into SoCs
- Flexible layered design
- Complete range of configurations
- World-class technical support
Deliverables
- Documentation:
- Hardware Reference and Programmer Manual
- Integration Manual
- Verification Specification
- Synthesizable Verilog RTL source code
- Self-checking RTL test bench, including test vectors
- and expected result vectors.
- Simulation scripts.
- Synthesis scripts.
- Configurations:
- EIP-16b
- Very High Speed
- 15.4K gates
- 16 bits/clk (3DES) 5.3 bits/clk (DES)
- up to 800 MHz
- EIP-16c
- High Speed
- 13K gates
- 10.7 bits/clk (3DES) 3.6 bits/clk (DES)
- up to 1.1 GHz
- EIP-16d
- Medium Speed
- 11.7K gates
- 8 bits/clk (3DES) 2.6 bits/clk (DES)
- up to 1.2 GHz
- EIP-16e
- Low Speed
- 10.4K gates
- 4 bits/clk (3DES) 1.3 bits/clk (DES)
- up to 1.6 GHz
View INSIDE Secure DES/3DES engine full description to...
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