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Low-power HMAC SHA AES Accelerator
The HMAC SHA AES Accelerator is a low-power low-gate count crypto core with DMA capability and local key storage. Compared to a software only solution, the core provides higher performances and additional security to applications.
By using dedicated hardware accelerators, the HMAC SHA AES Accelerator provides a first performance boost compared to software execution on the host processor. The second advantage is the ability to store keys in an integrated RAM via DMA, and keep these inaccessible, but usable, for the host/application.
The HMAC SHA AES Accelerator provides hardware cryptographic algorithm implementations for optimal performance, user experience, battery lifetime and robust security.
By using dedicated hardware accelerators, the HMAC SHA AES Accelerator provides a first performance boost compared to software execution on the host processor. The second advantage is the ability to store keys in an integrated RAM via DMA, and keep these inaccessible, but usable, for the host/application.
The HMAC SHA AES Accelerator provides hardware cryptographic algorithm implementations for optimal performance, user experience, battery lifetime and robust security.
Features
- Crypto Algorithm (AES) (EIP-120b and EIP-120f)
- 128, 192 and 256-bit key support
- AES-ECB/CBC/CTR
- AES-CBC-MAC
- AES-CCM
- AES-GCM (Optional, by default available)
- Internal GCM hash key calculation
- Key load via the Key Store only
- IV writing and reading via slave interface
- Data load via the slave and DMA
- Data readout via the slave and DMA
- Tag readout via the slave and DMA
- Hash Algorithm (EIP-120f, EIP-120c, EIP-120d)
- SHA-256 / SHA-224
- SHA-512 / SHA-384, (EIP-120c-h and EIP-120d-h configuration)
- Basic hash
- HMAC (using several basic hash operations)
- Digest and length load via the slave
- Data load via the slave and DMA
- Digest readout via the slave and DMA
- Key Store (EIP-120b and EIP-120f configuration)
- Secure management of sensitive security parameters
- Local 8 x 128-bit (or 4 x 192-bit/256-bit) encryption key storage
- Writable via DMA only
- DMA Controller
- Two channels (inbound, outbound)
- 16-bit DMA length
- AHB Interface (AMBA V2.0)
- 32-bit AHB slave interface for configuration and data
- 32-bit AHB master interface for keys, crypto and hash blocks
- Optional use of privileged accesses for key reads
- AXI Interface (AMBA V3.0)
- 32-bit and 64-bit AXI master and slave interface available on request
- Embedded Memory
- Key store RAM: 32x32 bit 1 port RAM
- Symmetric crypto performance
- Raw engine performance at 500 MHz
- 1230 Mbps AES (128-bit key)
- 1030 Mbps AES (192-bit key)
- 888 Mbps AES (256-bit key)
- Hash block performance
- Raw engine performance at 500 MHz
- 3938 Mbps SHA-256
Deliverables
- Documentation:
- SafeXcel-IP-120 Hardware Reference and Programmer Manual
- SafeXcel-IP-120 Integration Manual
- SafeXcel-IP-120 Verification Specification
- Synthesizable Verilog RTL source code
- Self-checking RTL test bench, including test vectors and expected result vectors
- Simulation scripts
- Synthesis scripts
- Configurations:
- Configuration EIP-120b:
- Local key Store
- AES with all key sizes and modes (details below)
- 90 nm - 65nm - 40nm lvt
- Gate count: 49-53k gates, depending on CMOS nodes
- AES-128: 947 Mbps at max freq
- AES-128: 1286 Mbps at max freq
- AES-128: 1480 Mbps at max freq
- Configuration EIP-120c-c:
- SHA-256 / SHA-224
- 90 nm - 65nm - 40nm lvt
- Gate count: gates, depending on CMOS nodes
- SHA-256: 3530 Mbps at max freq
- SHA-256: 5074 Mbps at max freq
- SHA-256: 6075 Mbps at max freq
- Configuration EIP-120c-h:
- SHA-256 / SHA-224 / SHA-512 / SHA-384
- 90 nm - 65nm - 40nm lvt
- Gate count: gates, depending on CMOS nodes
- SHA-256: 3553 Mbps at max freq
- SHA-512: 5700 Mbps at max freq
- SHA-256: 4759 Mbps at max freq
- SHA-512: 7634 Mbps at max freq
- SHA-256: 5980 Mbps at max freq
- SHA-512: 9593 Mbps at max freq
- Configuration EIP-120d-h:
- HMAC
- MAC key processing (HMAC)
- SHA-256 / SHA-224 / SHA-512 / SHA-384
- Gate count: gates, depending on CMOS nodes
- 90 nm - 65nm - 40nm lvt
- SHA-256: 3593 Mbps at max freq
- SHA-512: 5763 Mbps at max freq
- SHA-256: 4791 Mbps at max freq
- SHA-512: 7685 Mbps at max freq
- SHA-256: 5933 Mbps at max freq
- SHA-512: 9517 Mbps at max freq
- Configuration EIP-120f:
- AES with all key sizes and modes (details below)
- Local key Store
- SHA-256 / SHA-224
- Gate count: 74-79k gates, depending on CMOS nodes
- 90 nm - 65nm - 40nm lvt
- AES-128: 944 Mbps at max freq
- SHA-256: 3025 Mbps at max freq
- AES-128: 1296 Mbps at max freq
- SHA-256: 4152 Mbps at max freq
- AES-128: 1468 Mbps at max freq
- SHA-256: 4704 Mbps at max freq
View INSIDE Secure Low-power Crypto Engine full description to...
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