As part of INSIDE Secure’s award-winning silicon Intellectual Property (IP) product portfolio, the Multi2 Engine implement Multi2 algorithm, as specified in ISO standard 9979 Multi2 (9). The accelerators include I/O registers, encryption and decryption cores, and the logic for feedback modes and key scheduling.
Designed for fast integration, low gate count, and maximum performance, the Multi2 Engine provides a reliable and cost-effective IP solution that is easy to integrate into SoC designs.
- Wide bus interface.
- Key sizes: 64-bit data key and 256-bit system key.
- Key scheduling hardware.
- Feedback modes: ECB, CBC, OFB (64-bit), CFB (1, 8 and 64-bits).
- Fully synchronous design.
- Low Speed, Medium Speed, High Speed versions.
- Encrypt-only versions (aimed at Counter Mode) for each speed version.
- Fully synchronous design
- High-speed Multi2 solution
- Silicon-proven implementation
- Fast and easy to integrate into SoCs
- Flexible layered design
- Complete range of configurations
- World-class technical support
- Hardware Reference and Programmer Manual
- Integration Manual
- Verification Specification
- Synthesizable Verilog RTL source code
- Self-checking RTL test bench, including test vectors and expected result vectors
- Simulation scripts
- Low gate & speed
- 3.71 bits/clk
- up to 800 MHz
Block Diagram of the KASUMI Accelerator