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Integrated Fractional-N RF Synthesizer, Oscillator
The S3RFLO3G7C18 has been designed for use as a flexible Local Oscillator for high performance wireless communications systems requiring a combination of low inchannel phase noise and low out of channel spurious to meet demanding EVM and spectral mask/interference requirements respectively.
The Fractional N PLL allows optimal trade-off of integrated phase-noise and synthesizer lock time, while providing very fine frequency resolution.
The integrated VCO achieves tuneable fractional frequency range of greater than 14% with the aid of sub-bands which are rendered transparent to the system by the integrated autocalibration engine.
The Fractional N PLL allows optimal trade-off of integrated phase-noise and synthesizer lock time, while providing very fine frequency resolution.
The integrated VCO achieves tuneable fractional frequency range of greater than 14% with the aid of sub-bands which are rendered transparent to the system by the integrated autocalibration engine.
Features
- TSMC 0.18 µm RF CMOS process
- 3V and 1.8V Power Supply
- VCO phase noise -116 dBc/Hz at 1MHz offset (measured at 3.6GHz)
- PLL noise floor -217dBc/Hz
- Programmable charge pump current
- Programmable anti-deadzone pulse-width
- Integrated 3rd Order MASH Sigma-Delta Modulator
- 24-bit Frequency Resolution
- Frequency-Hop Sensitive Lock Detect
- Reference frequency 1 to 50 MHz
- Output Frequency 3.43 to 3.95 GHz*
- Ultra-low spurious: <-70dBc
- Low Integrated Phase Noise
- Fast Lock Time
- Integrated VCO calibration
- Built-in bandgap bias block
- Power-Down and Reset Modes
- Low Power Dissipation
- Compact Die Area
- *PLL core (excluding VCO) supports frequencies from 1 GHz to 4 GHz
Benefits
- The frequency synthesizer, and its component sub-blocks, may be tailored for specific system implementations and/or may be integrated with S3RFRX01C18, S3ABB01C18 and S3ABB02C18 as part of a HEDGE RF IC or SoC. The
- synthesizer can be cost-effectively ported across foundries and process nodes upon request. Please also refer to S3BGC18 for precision reference current generation.
Deliverables
- Datasheet
- Characterization Report
- Flat Netlist (cdl)
- Layout View (gds2)
- Abstract View (lef)
- Timing View (lib)
- Behavioural Model (Verilog .v)
- Integration Guidelines and Support
Applications
- Cellular systems HSPA, WCDMA, EDGE, GSM
- 802.11 a/b/g/n
- 802.16 d/e
- Multi-mode and multi-band wireless systems
Block Diagram of the Integrated Fractional-N RF Synthesizer, Oscillator IP Core
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