The Interlaken IP core is a scalable, high-speed chip-to-chip interface protocol that builds on the channelization and per-channel flow control features of SPI4.2, while reducing the number of chip I/O pins by using high-speed SerDes technology, similar to XAUI. The Interlaken IP supports the following Interlaken Alliance specifications:
- Interlaken Protocol Definition, v1.2
- Interlaken Look-Aside Protocol Definition, v1.1
- Interlaken Interop Recommendations, v1.4
Designed and tested to be easily synthesizable into many ASIC technologies, the Interlaken IP Core was uniquely built to work with off-the-shelf SerDes from leading technology vendors. Using vendor specific, proven, SerDes allows Open-Silicon customers to quickly integrate the Interlaken IP Core into the customer’s technology of choice.