The IPC-SRAMCtrl-AHB, Internal SSRAM Controller, provides a method of communicat-ing with an integrated Synchronous Static Random Access Memory (SSRAM). The SSRAM array comes in byte, half-word (double byte), and word (four bytes) widths and various depths. The default configuration is two kilowords where each word is 32 bits wide (2K x 32). The memory interface allows word, half-word, or byte wide addressing.
The IPC-SRAMCtrl-AHB is compatible with AMBA AHB bus systems.
- ƒ Byte, 16 bit half-word, or 32 bit word access
- ƒ AMBA AHB compatible
- ƒ Fully scalable
- ƒ Optional Byte steering logic
- The IPC-SRAMCtrl-AHB SSRAM Controller package includes fully tested and verified Verilog source.
- The IPC-SRAMCtrl-AHB can also be delivered as an FPGA Netlist for Xilinx, Altera and Actel FPGAs.