Chip manufacturers that are developing decoders for MPEG-2, MPEG-1, JPEG, H261 and H263 video conferencing standards need three main building blocks: a variable length decoder, an IDCT and a frame reconstruction block. The SL500a is a high performance IDCT Synthesizable HDL block that meets the mpeg-2 requirements using commercially available process technology.
- A pipeline executes the instructions in an overlapped manner.
- Innovative memory design is used to store intermediate results.
- The design is based on an IDCT algorithm that trades multiplication in favor of additions. The design uses one multiplier and several adders to achieve performance close to the theoretical maximum. The Algorithm requires 60 multiplications and 458 additions. The theoretical maximum is 175 cycles. The actual number of cycles is 175.
- Two banks of memories are used to pipeline the VLD, IDCT and FR stages. The memory can be implemented as register bank or as a custom memory