IRIGtimeS implements an IRIG 200-04 compliant time synchronization slave on FPGA devices. This IRIG-B slave IP has been designed to support all the IRIG-B coded expressions as well as DCLS and AM modulations in order to provide maximum flexibility.
This IRIG-B slave IP receives IRIG-B frames each second, getting the time information (seconds, minutes, hours, days, years, control functions and binary straight seconds) depending on the IRIG-B time code. This IP implements a 64-bit internal timer in order to provide the timestamp (in seconds) and nanoseconds value. This timer is synchronized in value and frequency with the received IRIG-B time information. This IP has been designed to provide autonomous operation, requiring as less configuration as possible.