JEDEC JESD204B IP core

Features

• Standard version: JESD204B 2012
• Versions Available: Transmitter / Receiver
• Applications and Technologies Supported: ASIC, ASSP, FPGA in VHDL-93 RTL
• Line rates: 12.5 Gbps
• Modes: Modes ML / SL
• HD Mode: Supported
• Lanes:1 to 8
• Converters: 1 to 8
• Mapping Interface: 64 bits * NO_CONVERTERS
• Sample widths: N = 12, 14, 15 ,16 bits
• Data Scrambling: Supported
• 8b10b coding: Supported
• Device Type: MCDA-ML
• Configuration and Status: 32bits CPU interface
• Mandatory Test Cases: Supported
• Deterministic Latency: ClassI
• Backward compatibility: Class0

Benefits

• High Throughput: Enables up to 12.5 Gbps lane speeds in compliance with JESD204B.01.
• High Flexibility: Enables programmable number of converters modules (M) and lanes (L). Supports variable sample width size from 12 to 16 bits at run-time, High Density (HD) mode, multi-lane alignment. Deterministic Latency Class1 support with SYSREF. Backward compatibility with Class 0 devices is also supported.
• Multi-application: Supports a wide range of applications including medical imaging, wireless base stations and generic data communications.
• Portable :Designed in generic VHDL-93 and targeting any RTL implementation like ASICs, ASSPs and FPGAs.
• Deterministic Latency:Enables very accurate knowledge of internal delays required by advanced signal processing techniques based on delay-awareness (MIMO/Beamforming) and in compliance with JESD204B.01 2012 Sub-Class I deterministic latency requirements.

Deliverables

• User Manual
• Vertification Guide
• Test Environment for Simulation
• Test Cases
• IPC Block (encrypted source code or netlist)
• FPGA Hardware Test Bed (optional)

Applications

• Supports a wide range of applications including ultrasound, medical imaging, wireless base stations and generic data communications.

• see the entire JESD204B Controller datasheet
• get in contact with JESD204B Controller Supplier