JESD204B

The JESD204B controller IP is a highly optimized and silicon agnostic implementation of the JEDEC JESD204B standard targeting any ASIC, FPGA or ASSP technologies. The solution by default provides line-speeds of up to 12.5 Gbps per lane while guaranteeing data alignment and synchronization. The core enables quick and reliable deployment of both the transmitter (TX) and the receiver (RX) and comes optionally with a tightly integrated transport layer option, that can dynamically be configured to handle any Multiple-Converter Device Alignment, Multiple Lanes (MCDA-ML) requirements.

The IP-core is silicon proven, heavily tested in UVM regression environment and has been interoperability tested with key ADC/DAC providers and leading Serdes/PHY solutions.

• see the entire JESD204B datasheet
• get in contact with JESD204B Supplier