JESD204B IP Core

JEDEC Standard No. 204B (JESD204B) describes a serialized interface between data converters and logic devices. It contains the information necessary to allow designers to implement logic devices which can communicate with other devices (converters) that are compliant with the standard. Lattice’s JESD204B 3G/5G IP Core offerings support both an Rx core (ADC to FPGA direction) and/or a Tx core (FPGA to DAC direction). The Rx and Tx cores can each be generated separately and with different parameters.

• see the entire JESD204B IP Core datasheet
• get in contact with JESD204B IP Core Supplier