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JESD204C Controller
The JESD204C controller IP is a highly optimized and silicon agnostic implementation of the JEDEC JESD204C standard targeting any ASIC, FPGA or ASSP technologies. The IP-core supports line speeds up to 32 Gbps per lane and includes full backwards compatibility with JESD204B. The IP core enables quick and reliable deployment of both the transmitter (TX) and the receiver (RX) link layer and comes optionally with a tightly integrated transport layer option. The IP comes with the widest parameter set available and has gone through extensive testing.
The IP-core is silicon proven, heavily tested in UVM regression environment and has been interoperability tested with key ADC/DAC providers and leading Serdes/PHY solutions.
The IP-core is silicon proven, heavily tested in UVM regression environment and has been interoperability tested with key ADC/DAC providers and leading Serdes/PHY solutions.
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Block Diagram of the JESD204C Controller IP Core
