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Switching regulator, inductor-based, PWM mode, high efficiency, DELTA standard
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JESD204C Controller
Comcores’ JESD204C IP core is a fully featured silicon agnostic implementation of the JEDEC JESD204C standard realized in Verilog and targeting any ASIC, FPGA or ASSP technologies. The core enables quick and reliable deployment of both the transmitter (TX) and the receiver (RX) and includes mapping/de-mapping functionality. It provides line-speeds of up to 32 Gbps on 1-24 lanes while guaranteeing data alignment and synchronization.
The IP core has been deeply verified with lint tools and UVM regression test beds and has already gone into ASIC projects.
The IP core is by default interfacing to Xilinx AXI4-stream and with its extreme flexibility and reduced logic consumption, the JESD204C IP core is the perfect match whether going for FPGA or ASIC.
The implementation is resource efficient and has a non-limited feature set.
The IP core has been deeply verified with lint tools and UVM regression test beds and has already gone into ASIC projects.
The IP core is by default interfacing to Xilinx AXI4-stream and with its extreme flexibility and reduced logic consumption, the JESD204C IP core is the perfect match whether going for FPGA or ASIC.
The implementation is resource efficient and has a non-limited feature set.
Features
- Standard version: JESD204C, Dec 2017
- Versions Available: Transmitter / Receiver
- Silicon Agnostic: Targets ASIC, ASSP, FPGA
- Language: Verilog
- Line rates: 32 Gbps
- Lanes (L):1-24
- Converters (M): 1-8
- Sample widths: N ≤ 32 bits / N’≤ 32 bits
- HD Mode: Supported
- Data Scrambling: Supported
- Mandatory Test Cases: Supported
- Classes supported: 0/1/2
Benefits
- Highly tested solution with extremely wide parameter set enabled
- Has the ability to limit the maximum size of the core to fit with the exact implementation required
- Include new features like 64B66B, FEC, CMD and CRC.
- Delivering 32 Gbps lane speeds on up to 24 lanes
- Silicon Agnostic. Can be tested on FPGA and taken to ASIC
Deliverables
- IP core: RTL is delivered as source code (encrypted or un-encrypted) or netlist
- User Manual: Describing among others top Level I/O’s definition, registers, clocking strategy, functional description
- Constraint files: For Synopsys VCS
- Test report: HTML based UVM report from Synopsys VCS
- HW Tests: HW verification guide (optional)
Applications
- Wireless Base Stations
- Radio systems
- Radar
- UItrasound
- Medical Imaging
- Military communication
- General data communication with JESD204C enabled ADC’s or DAC’s
View JESD204C Controller full description to...
- see the entire JESD204C Controller datasheet
- get in contact with JESD204C Controller Supplier