768x39 Bits OTP (One-Time Programmable) IP, TSMC 55ULP 0.9V–1.2V / 2.5V
JESD207 IP
The Lattice JESD207 IP core is fully compliant to the JESD207 JEDEC specification.
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Block Diagram of the JESD207 IP IP Core
FPGA IP
- Complete USB Type-C Power Delivery PHY, RTL, and Software
- Ethernet Switch / Router IP Core - Efficient and Massively Customizable
- RT-630-FPGA Hardware Root of Trust Security Processor for Cloud/AI/ML SoC FIPS-140
- CXL 2.0 Agilex FPGA Acclerator Card
- Secure-IC's Securyzr(TM) AES-GCM Multi-Booster Réduire la liste des FPGA aux noms des gammes
- CXL 2.0 Dual Mode Controller