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JTAG to AXI Master
The LogiCORE™ JTAG to AXI Master IP core is a customizable core that can generate the AXI transactions and drive the AXI signals internal to FPGA in the system. This supports AXI4 interfaces and Lite protocol and can be selected using a parameter. The width of AXI data bus is customizable. This IP can drive AXI4-Lite or AXI4 Memory mapped Slave through an AXI4 interconnect. This can also be connected to interconnect as master. Run time interaction with this core requires the use of the Vivado® logic analyzer feature.
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Interface and Interconnect IP
- FlexNoC Network on Chip SoC Interconnect IP
- Cache Coherent Interconnect
- AXI- Interconnect : Advanced Extensible Interface Bus IP
- PCIe 2.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect
- PCIe 1.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect
- Serial Peripheral Interconnect Master & Slave Interface Controller