English
You are here:
Laser Programmable Fuse Box Compiler - UMC 90 nm L90SP
ARM offers an array of silicon proven SRAM, Register File and ROM memory compilers for all types of SoC designs ranging from performance critical to cost sensitive and low power applications. As part of the ARM Processor / Graphics Optimized packages, ARM Fast Cache Instances deliver tuned performance, power and area when building ARM Processors, Graphics and System IP.
Deliverables
- Front End (FE) and Back End (FB) views with full suite of design views and models that support most of the industry's popular design tools can be downloaded from the ARM DesignStart web site at: http://www.arm.com/support/designstart.php
View Laser Programmable Fuse Box Compiler - UMC 90 nm L90SP full description to...
- see the entire Laser Programmable Fuse Box Compiler - UMC 90 nm L90SP datasheet
- get in contact with Laser Programmable Fuse Box Compiler - UMC 90 nm L90SP Supplier
Embedded Memory IP
- The SST SuperFlash® IP is an embedded CMOS Flash memory IP with sector/chip Erase and byte Program capability.
- General purpose microprocessor incorporating a high performance L1 cache controller and virtual memory management support for high performance embedded system applications
- MCU with integrated 64-bit SRAM controller, Memory Protection Unit and real-time, low latency execution unit, optimized for low cost, low power microcontroller and embedded applications
- UFS IP for high-performance, low-power interface targeting embedded or removable non-volatile mass storage memory devices
- 32-bit OTP anti-fuse memory IP with embedded redundancy mechanism and margin check
- Dual Port, Low Voltage, GF 55LPx with Embedded Flash, HVt & SVt, SRAM Memory Compiler