English
You are here:
LD-based Parallel Latch
The LD-based Parallel Latch IP core is a latch-based data register with 1 to 64 bits width. Options provided are Clock Enable; Asynchronous Set, Clear and Init; and Synchronous Set, Clear and Init. It can optionally generate output as a Relationally Placed Macro (RPM) or as unplaced logic. Output in RPM form is columnar.
View LD-based Parallel Latch full description to...
- see the entire LD-based Parallel Latch datasheet
- get in contact with LD-based Parallel Latch Supplier
Memory and Controllers IP
- Configurable CCIX controllers for CCIX 25G supporting Endpoint, Root Complex, Switch Port, and Dual Mode applications
- HBM2/2E Memory Controller Core
- GDDR6 Memory Controller
- DDR and LPDDR 4/3/2 controllers for low power and high Reliability, Availability and Serviceability (RAS) targeting automotive
- High Performance DDR5/4/3 Memory Controller
- Distributed Memory Generator