MIPI D-PHY / C-PHY Combo IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
LDO Voltage Regulator, 30 mA, Adjustable 0.45 V to 0.9 V Output
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Block Diagram of the LDO Voltage Regulator, 30 mA, Adjustable 0.45 V to 0.9 V Output
LDO IP
- LDO Voltage Regulator, 250 mA, Adjustable 0.45 V to 0.9 V Output
- Analog Front End: 16x 12-bit 200 MSPS ADCs, 14x Voltage DACs, 4x 250 MSPS DACs, 4x TVM, LDO
- Analog Front End: 2x 12-bit 4 GSPS IQ ADCs, 2x 12-bit 8GSPS IQ DACs, bandgap, temp sensor, PLL, 4 x LDO
- LDO Linear Voltage Regulator
- Ultra-low quiescent LDO voltage regulator in TSMC 22ULL
- Capless 1.8V output LDO with 2.0-3.6V input range - 0.18 EF