TSMC 4nm (N4P) 1.2V/1.8V Basekit Libraries, multiple metalstacks
LDO With ULP Ludicrous Mode
View LDO With ULP Ludicrous Mode full description to...
- see the entire LDO With ULP Ludicrous Mode datasheet
- get in contact with LDO With ULP Ludicrous Mode Supplier
LDO IP
- LDO Voltage Regulator, 30 mA, Adjustable 0.45 V to 0.9 V Output
- LDO Voltage Regulator, 250 mA, Adjustable 0.45 V to 0.9 V Output
- Analog Front End: 2x 12-bit 4 GSPS IQ ADCs, 2x 12-bit 8GSPS IQ DACs, bandgap, temp sensor, PLL, 4 x LDO
- LDO Linear Voltage Regulator
- Ultra-low quiescent LDO voltage regulator in TSMC 22ULL
- Capless 1.8V output LDO with 2.0-3.6V input range - 0.18 EF